1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which has a standby mode and an active mode.
2. Description of the Background Art
Conventionally, an eDRAM on which a logic circuit and a DRAM are embedded on the same chip has a dual-oxide structure. In the dual-oxide structure, a circuit driven by an external power supply voltage VDDH, which is a relatively high voltage, for a DRAM, consists of thick film transistors, and a circuit driven by a power supply voltage, which is a relatively low voltage for a logic circuit, consists of thin film transistors. In addition, an external power supply voltage VDDH is lowered to generate an internal power supply voltage VDDS for sense amplifiers, a bit line precharge voltage VBL=VDDS/2 is generated from internal power supply voltage VDDS, and each sense amplifier consists of thin film transistors to accelerate operating rate and decrease power consumption.
FIG. 28 is a block diagram which shows the important parts of a DRAM of this type. In FIG. 28, the DRAM includes a standby VDDS generation circuit 130, a signal generation circuit 131, and an active VDDS generation circuit 132. Standby VDDS generation circuit 130 has a relatively low current driving force, is always activated, is driven by external power supply voltage VDDH, and supplies a current to an internal power supply voltage potential VDDS line so that internal power supply potential VDDS becomes equal to a reference potential VR.
Signal generation circuit 131 sets a signal ACTVDCE at “H” level when a signal φACT is set at “H” level, and sets ACTVDCE at “L” level when a signal φPRE is set at “H” level. Signal φACT is a signal which is set at “H” level in response to an active command ACT, and signal φPRE is a signal which is set at “L” level in response to a precharge command PRE.
Active VDDS generation circuit 132 has a relatively high current driving force, is activated only while output signal ACTVDCE of signal generation circuit 131 is at “H” level, is driven by external power supply voltage VDDH, and supplies a current to the internal power supply potential VDDS line so that internal power supply potential VDDS becomes equal to reference potential VR.
Therefore, a current is supplied from standby VDDS generation circuit 130 in a standby period in which power consumption is low and a current is supplied from both standby VDDS generation circuit 130 and active VDDS generation circuit 132 in an active period in which power consumption is high, thereby keeping internal power supply potential VDDS equal to reference potential VR.
FIG. 29 is a circuit diagram which shows the configuration of standby VDDS generation circuit 130. In FIG. 29, standby VDDS generation circuit 130 includes P-channel MOS transistors 140 to 142 and N-channel MOS transistors 143 to 145. P-channel MOS transistors 141 and 142 are connected between an external power supply potential VDDH line and nodes N141, N142, respectively, and the gates thereof are both connected to node N142. P-channel MOS transistors 141 and 142 constitute a current mirror circuit.
N-channel MOS transistors 143 and 144 are connected between nodes N141, N142 and a node N143, respectively, and the gates thereof receive reference potential VR and internal power supply potential VDDS, respectively. N-channel MOS transistor 145 is connected between node N143 and a ground potential GND line and the gate thereof receives a bias voltage VB. A constant pass current Ib flows in N-channel MOS transistor 145. MOS transistors 141 to 145 constitute a differential amplifier. P-channel MOS transistor 140 is connected between the external power supply potential VDDH line and an internal power supply potential VDDS line and the gate thereof is connected to node N141.
If internal power supply potential VDDS is lower than reference potential VR, then a current which flows in P-channel MOS transistor 141 becomes lower than a current which flows in N-channel MOS transistor 143, the level of node N141 is lowered to “L” level and P-channel MOS transistor 140 becomes conductive. As a result, a current is supplied from the external power supply potential VDDH line to the internal power supply potential VDDS line through P-channel MOS transistor 140, and internal power supply potential VDDS rises. If internal power supply potential VDDS is higher than reference potential VR, then the current which flows in P-channel MOS transistor 141 becomes higher than the current which flows in N-channel MOS transistor 143, the level of node N141 is raised to “H” level and P-channel MOS transistor 140 becomes nonconductive. If internal power supply potential VDDS is consumed, internal power supply potential VDDS lowers. Accordingly, internal power supply potential is kept equal to reference potential VR.
FIG. 30 is a circuit diagram which shows the configuration of a VBL generation circuit 150 which generates bit line precharge potential VBL which is a half of internal power supply potential VDDS. In FIG. 30, VBL generation circuit 150 includes resistance elements 151 and 152, N-channel MOS transistors 153 and 154, and P-channel MOS transistors 155 and 156. Resistance element 151, N-channel MOS transistor 153, P-channel MOS transistor 155 and resistance element 152 are connected in series between an internal power supply potential VDDS line and a ground potential GND line. The gate of N-channel MOS transistor 153 is connected to the drain thereof (a node N151), the gate of P-channel MOS transistor 155 is connected to the drain thereof (a node N152). Each of MOS transistors 153 and 155 constitute a diode element.
N-channel MOS transistor 154 and P-channel MOS transistor 156 are connected between an external power supply potential VDDH line and the ground potential GND line and the gates thereof are connected to nodes N151 and N152, respectively. A node N154 between MOS transistors 154 and 156 is connected to a bit line precharge potential VBL line. To prevent the transistors from being broken by external power supply voltage VDDH, each of MOS transistors 153 to 156 is formed into a thick film transistor having a thick gate oxide film.
The resistance values of resistance elements 151 and 152 and the sizes of MOS transistors 153 and 155 are set so that the potential of a node N153 between MOS transistors 153 and 155 becomes VDDS/2. If it is assumed that the threshold voltage of an N-channel MOS transistor is Vthn and that of a P-channel MOS transistor is Vthp, the potentials of nodes N151 and N152 are VDDS/2+Vthn and VDDS/2−Vthp, respectively. Therefore, potential VBL of node N154 is VDDS/2.
However, if internal power supply potential VDDS is lowered to approximately 1.2 to 1.5 V, it is difficult for VBL generation circuit 150 shown in FIG. 30 to generate bit line precharge potential VBL. This is because threshold voltage Vthp of P-channel MOS transistor 155 which is a thick film transistor is 0.8 V and the potential of node N153 cannot be made lower than threshold voltage Vthp of P-channel MOS transistor 155.
Under these circumstances, a VBL generation circuit 160 capable of generating bit line precharge potential VBL even if internal power supply potential VDDS is lowered, has been proposed. As shown in FIG. 31, VBL generation circuit 160 is constituted so that N-channel MOS transistors 153 and 154 and P-channel MOS transistors 155 and 156 are replaced by N-channel MOS transistors 163 and 164 and P-channel MOS transistors 165 and 166, respectively, and that internal power supply potential VDDS is applied to the drain of N-channel MOS transistor 164. Each of MOS transistors 163 to 166 are constituted out of a thin film transistor having a thin gate oxide film and has a threshold voltage (approximately 0.4 to 0.5 V) lower than that of a thick film transistor. The reason for applying internal power supply potential VDDS instead of external power supply potential VDDH to the drain of N-channel MOS transistor 164 is to prevent MOS transistors 164 and 166 from being broken by external power supply potential VDDH. According to VBL generation circuit 160, even if internal power supply voltage VDDS is lowered, it is possible to set the potential of node N153 between MOS transistors 163 and 165 higher than threshold voltage Vthp of P-channel MOS transistor 165, to generate bit line precharge potential VBL and to generate cell plate potential VCP by the same circuit as VBL generation circuit 160.
Nevertheless, if VBL generation circuit 160 is employed, the load capacitance of internal power supply potential VDDS disadvantageously increases, making internal power supply potential VDDS unstable. Namely, as shown in FIG. 29, if internal power supply potential VDDS is lower than reference potential VR, the potential of node N141 decreases and a current is supplied from the external power supply VDDH line to the internal power supply potential VDDS line through P-channel MOS transistor 140 until internal power supply potential VDDS becomes equal in level to reference potential VR. If it is assumed herein that the potential change of node N141 is ΔV and the gate capacitance of P-channel MOS transistor 140 is C, then time T for lowering the potential of node N141 by ΔV is expressed as T=ΔVC/Ib (sec). In a standby mode, internal power supply potential VDDS is hardly consumed. Due to this, the size of P-channel MOS transistor 140 is set small. If P-channel MOS transistor 140 is made large in size, gate capacitance C increases and the response of standby VDDS generation circuit 130 deteriorates. The size of P-channel MOS transistor 140 is, therefore, optimized to a size according to pass current Ib.
In a standby mode, internal power supply potential VDDS is hardly consumed and the quantity of charge to be supplied through P-channel MOS transistor 140 is small, so that potential change ΔV of node N141 may be small. Due to this, time T for lowering the potential N141 may be short (T<0.1 ms) and the charge supply capability and response of the circuit are not adversely influenced. In addition, when a potential is applied, the internal power supply potential VDDS line is charged by this standby VDDS generation circuit 130. However, unless internal power supply potential VDDS is used as a current supply source for the VBL generation circuit and the VCP generation circuit, internal power supply potential VDDS is not consumed. As a result, it is possible to raise internal power supply potential VDDS in short time which is approximately equal to power-on time (200 μs) without causing any problem.
However, if internal power supply potential VDDS is used as a current supply source for the VBL generation circuit and the VCP generation circuit, power is greatly consumed when a potential is applied. Due to this, it is necessary to increase potential change ΔV of node N141 to carry high current to P-channel MOS transistor 140. If potential change ΔV is set at approximately 2 V, time T=ΔVS/Ib becomes not less than several nanoseconds. Further, if internal power supply potential VDDS reaches reference potential VR, it is necessary to return the level of node N141 to “H” level. To do so, it is also necessary to take a time of not less than several nanoseconds, similar to a case where internal power supply potential VDDS becomes lower than reference potential VR.
In this way, an operation that the VDDS generation circuit cannot respond in not less than several nanoseconds since internal power supply potential VDDS becomes lower than reference potential VR and internal power supply potential VDDS is thereby lowered and the VDDS generation circuit cannot respond in not less than several nanoseconds since internal power supply potential VDDS becomes higher than reference potential VR and internal power supply potential VDDS thereby rises, are repeatedly carried out. Consequently, as shown in FIG. 32, internal potentials VDDS and VBL disadvantageously become unstable and ring.
Moreover, in DRAM, a negative potential VBB is applied to the back gates of N-channel MOS transistors of each memory cell so as to improve the refresh characteristic of the memory cell. However, a parasitic capacitance exists between a negative potential VBB line and an internal power supply potential VDDS line. Due to this, if internal power supply potential VDDS ring, negative power supply potential VBB ring, as well, with the result that the potential of the negative potential VBB line becomes positive and latch-up may possibly occur.
Furthermore, if P-channel MOS transistor 140 is made large in size to thereby improve the current supply capability, the ringing of internal power supply potential VDDS can be suppressed. However, gate capacitance C of P-channel MOS transistor 140 increases. It is, therefore, necessary to increase pass current Ib so as not to deteriorate response, with the result that a standby current, disadvantageously, greatly increases.